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Am42BDS6408H
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 30491 Revision A
Amendment +3 Issue Date October 23, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am42BDS6408H
Am29BDS640H 64 Megabit (4 M x 16-Bit) Stacked MultiChip Package (MCP) Flash Memory and SRAM CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM
FLASH DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 0.13 m process technology VersatileIOTM (VIO) Feature -- Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin -- 1.8V compatible I/O signals -- Contact factory for availability of 1.5V compatible I/O signals
Simultaneous Read/Write operation
PERFORMANCE CHARCTERISTICS
Read access times at 66/54 MHz (CL=30 pF)
-- Burst access times of 11/13.5 ns at industrial temperature range -- Synchronous latency of 56/69 ns -- Asynchronous random access times of 45/50/55 ns Power dissipation (typical values, CL = 30 pF) -- Burst Mode Read: 10 mA -- Simultaneous Operation: 25 mA -- Program/Erase: 15 mA -- Standby mode: 0.2 A
-- Data can be continuously read from one bank while executing erase/program functions in other bank -- Zero latency between read and write operations -- Four bank architecture: 8Mb/24Mb/24Mb/8Mb
Programable Burst Interface
HARDWARE FEATURES
Handshaking feature -- Provides host system with minimum possible latency by monitoring RDY -- Reduced Wait-state handshaking option further reduces initial access cycles required for burst accesses beginning on even addresses Hardware reset input (RESET#) -- Hardware method to reset the device for reading array data WP# input -- Write protect (WP#) function allows protection of the four highest and four lowest 4 kWord boot sectors, regardless of sector protect status Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level Password Sector Protection -- A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ACC input: Acceleration function reduces programming time; all sectors locked when ACC = VIL
-- 2 Modes of Burst Read Operation -- Linear Burst: 8, 16, and 32 words with wrap-around
-- Continuous Sequential Burst
SecSiTM (Secured Silicon) Sector region
-- Up to 128 words accessible through a command sequence -- Up to 64 factory-locked words -- Up to 64 customer-lockable words
Sector Architecture
-- Sixteen 4 Kword sectors and one hundred twenty-six 32 Kword sectors -- Banks A and D each contain eight 4 Kword sectors and fifteen 32 Kword sectors; Banks B and C each contain forty-eight 32 Kword sectors -- Sixteen 4 Kword boot sectors: eight at the top of the address range and eight at the bottom of the address range Minimum 1 million erase cycle guarantee per sector 20-year data retention at 125C -- Reliable operation for the life of the system 89-ball FBGA package
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 30491 Rev: A Amendment:+3 Issue Date: October 23, 2003
Refer to AMD's Website (www.amd.com) for the latest information.
ADVANCE
INFORMATION
Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences Burst Suspend/Resume -- Suspends a burst operation to allow system use of the address and data bus, than resumes the burst at the previous state
CMOS compatible inputs, CMOS compatible outputs Low VCC write inhibit
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI) Software command set compatible with JEDEC 42.4 standards -- Backwards compatible with Am29F and Am29LV families Data# Polling and toggle bits -- Provides a software method of detecting program and erase operation completion Erase Suspend/Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
SRAM FEATURES
Power dissipation -- Operating: 10 mA typical -- Standby: 2 A CE1s# and CE2 Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 1.0 to 2.2 volt Byte data control: LB# (DQ7-DQ0), UB#s (DQ15-DQ8)
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Am42BDS6408H
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ADVANCE
INFORMATION
GENERAL DESCRIPTION
The Am29BDS640H is a 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 4,194,304 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0-volt VHH on ACC may be used for faster program performance if desired. At 66 MHz, the device provides a burst access of 11 ns at 30 pF with a latency of 56 ns at 30 pF.At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 69ns at 30 pF. The device operates within the industrial temperature range of -40C to +85C. The device is offered in the 64-ball FBGA package. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Bank A 15 B C D 8 4 Kwords 48 48 15 32 Kwords 32 Kwords 32 Kwords 32 Kwords Quantity 8 Size 4 Kwords dresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a program or erase operation is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. When at VIL , WP# locks the four highest and four lowest boot sectors. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The active clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad-
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ADVANCE
INFORMATION
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 7 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 9
Special Handling Instructions for FBGA Package ..........................9
Table 10. Sector Address Table ........................................................... 26
Command Definitions . . . . . . . . . . . . . . . . . . . . . 30
Reading Array Data ...................................................................... 30 Set Configuration Register Command Sequence ........................ 30
Figure 3. Synchronous/Asynchronous State Diagram.......................... 30
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 11 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 12
Table 1. Device Bus Operations ..........................................................12
Read Mode Setting ...................................................................... 30 Programmable Wait State Configuration ...................................... 30
Table 11. Programmable Wait State Settings ....................................... 31
Reduced Wait-state Handshaking Option .................................... 31
Table 12. Wait States for Reduced wait-state Handshaking ............... 32
VersatileIOTM (VIO) Control .......................................................... 12 Requirements for Asynchronous Read Operation (Non-Burst) ..................................................................12 Requirements for Synchronous (Burst) Read Operation ............. 12 8-, 16-, and 32-Word Linear Burst with Wrap Around .................. 13
Table 2. Burst Address Groups .............................................................13
Standard Handshaking Option ..................................................... 32
Table 13. Wait States for Standard Handshaking ................................. 32
Read Mode Configuration ............................................................ 32
Table 14. Read Mode Settings ............................................................. 33
Burst Suspend/Resume ............................................................... 13 Configuration Register ................................................................. 14 Reduced Wait-state Handshaking Option ....................................14 Simultaneous Read/Write Operations with Zero Latency ............ 14 Writing Commands/Command Sequences .................................. 14 Accelerated Program Operation ...................................................15
Table 3. Am42BDS6408H Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................................................16
Burst Active Clock Edge Configuration ........................................ 33 RDY Configuration ....................................................................... 33
Table 15. Configuration Register .......................................................... 33
Reset Command .......................................................................... 33 Autoselect Command Sequence .................................................. 34 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence ................................................................... 34 Program Command Sequence ..................................................... 34 Unlock Bypass Command Sequence ........................................... 35
Figure 4. Program Operation ................................................................ 35
Sector/Sector Block Protection and Unprotection ........................16 Sector Protection ..........................................................................16 Selecting a Sector Protection Mode .............................................16 Persistent Sector Protection ......................................................... 17 Persistent Protection Bit (PPB) ....................................................17 Persistent Protection Bit Lock (PPB Lock) ................................... 17 Dynamic Protection Bit (DYB) ......................................................17
Table 4. Sector Protection Schemes .....................................................18
Chip Erase Command Sequence ................................................. 35 Sector Erase Command Sequence .............................................. 36 Erase Suspend/Erase Resume Commands ................................ 36
Figure 5. Erase Operation .................................................................... 37
Persistent Sector Protection Mode Locking Bit ............................ 18 Password Protection Mode .......................................................... 18 Password and Password Mode Locking Bit ................................. 19 64-bit Password ...........................................................................19 Persistent Protection Bit Lock ......................................................19 High Voltage Sector Protection ....................................................19 Standby Mode .............................................................................. 19 Automatic Sleep Mode ................................................................. 20 RESET#: Hardware Reset Input .................................................. 20 Output Disable Mode ...................................................................20
Figure 1. Temporary Sector Unprotect Operation................................. 20 Figure 2. In-System Sector Protection/ Sector Unprotection Algorithms ............................................................ 21
Password Program Command ..................................................... 37 Password Verify Command .......................................................... 37 Password Protection Mode Locking Bit Program Command ....... 37 Persistent Sector Protection Mode Locking Bit Program Command 38 SecSi Sector Protection Bit Program Command .......................... 38 PPB Lock Bit Set Command ........................................................ 38 DYB Write Command ................................................................... 38 Password Unlock Command ........................................................ 38 PPB Program Command .............................................................. 38 All PPB Erase Command ............................................................. 39 DYB Write Command ................................................................... 39 PPB Status Command ................................................................. 39 PPB Lock Bit Status Command ................................................... 39 DYB Status Command ................................................................. 39 Command Definitions ................................................................... 40
Table 16. Command Definitions .......................................................... 40
SecSiTM (Secured Silicon) Sector Flash Memory Region ..................................................................22 Factory-Locked Area (64 words) .................................................. 22
Table 5. SecSi
TM
Write Operation Status . . . . . . . . . . . . . . . . . . . . 43
DQ7: Data# Polling ...................................................................... 43
Figure 6. Data# Polling Algorithm ......................................................... 43
Sector Addresses .....................................................22
Customer-Lockable Area (64 words) ........................................... 22 SecSi Sector Protection Bits ........................................................ 22 Hardware Data Protection ............................................................22 Write Protect (WP#) .....................................................................23 Low VCC Write Inhibit ...................................................................23 Write Pulse "Glitch" Protection .....................................................23 Logical Inhibit ............................................................................... 23 Power-Up Write Inhibit ................................................................. 23
Table 6. CFI Query Identification String ................................................23 Table 7. System Interface String........................................................... 24 Table 8. Device Geometry Definition .................................................... 24 Table 9. Primary Vendor-Specific Extended Query ..............................25
DQ6: Toggle Bit I .......................................................................... 44
Figure 7. Toggle Bit Algorithm .............................................................. 45
..................................................................................................... 45 DQ2: Toggle Bit II ......................................................................... 45
Table 17. DQ6 and DQ2 Indications ..................................................... 46
Reading Toggle Bits DQ6/DQ2 .................................................... 46 DQ5: Exceeded Timing Limits ...................................................... 46 DQ3: Sector Erase Timer ............................................................. 46
Table 18. Write Operation Status ......................................................... 47
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 48
Figure 8. Maximum Negative Overshoot Waveform............................. 48 Figure 9. Maximum Positive Overshoot Waveform .............................. 48
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INFORMATION
Figure 30. Reset Timings...................................................................... 64
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 48 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 49 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 49 SRAM DC and Operating Characteristics . . . . . . 50 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 10. Test Setup............................................................................ 51 Table 19. Test Specifications ................................................................51
Erase/Program Operations (VIO = 1.8 V) ..................................... 65
Figure 31. Asynchronous Program Operation Timings: AVD# Latched Addresses ................................................................................................. 66 Figure 32. Asynchronous Program Operation Timings: WE# Latched Addresses ................................................................................................. 67 Figure 33. Synchronous Program Operation Timings: WE# Latched Addresses ................................................................................................. 68 Figure 34. Synchronous Program Operation Timings: CLK Latched Addresses ................................................................................................. 69 Figure 35. Chip/Sector Erase Command Sequence............................. 70 Figure 36. Accelerated Unlock Bypass Programming Timing .............. 71 Figure 37. Data# Polling Timings (During Embedded Algorithm) ......... 72 Figure 38. Toggle Bit Timings (During Embedded Algorithm) .............. 72 Figure 39. Synchronous Data Polling Timings/Toggle Bit Timings....... 73 Figure 40. DQ2 vs. DQ6 ....................................................................... 73
Key to Switching Waveforms . . . . . . . . . . . . . . . 51 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 51
Figure 11. Input Waveforms and Measurement Levels ........................ 51
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52
VCC Power-up .............................................................................. 52
Figure 12. VCC Power-up Diagram ....................................................... 52
Synchronous/Burst Read (VIO = 1.8 V) ........................................ 53
Figure 13. CLK Synchronous Burst Mode Read (rising active CLK)..... 54 Figure 14. CLK Synchronous Burst Mode Read (Falling Active Clock) 54 Figure 15. Synchronous Burst Mode Read ........................................... 55 Figure 16. 8-word Linear Burst with Wrap Around ................................ 55 Figure 17. Linear Burst with RDY Set One Cycle Before Data ............. 56 Figure 18. Reduced Wait-state Handshake Burst Suspend/Resume at an even address......................................................................................... 57 Figure 19. Reduced Wait-state Handshake Burst Suspend/Resume at an odd address .......................................................................................... 57 Figure 20. Reduced Wait-state Handshake Burst Suspend/Resume at address 3Eh (or offset from 3Eh) .............................................................. 58 Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at address 3Fh (or offset from 3Fh by a multiple of 64) ................................ 58 Figure 22. Standard Handshake Burst Suspend prior to Initial Access 59 Figure 23. Standard Handshake Burst Suspend at or after Inital Access .. 59 Figure 24. Standard Handshake Burst Suspend at address 3Fh (starting address 3Dh or earlier) ......................................................................... 60 Figure 25. Standard Handshake Burst Suspend at address 3Eh/3Fh (without a valid Initial Access)....................................................................... 60 Figure 26. Standard Handshake Burst Suspend at address 3Eh/3Fh (with 1 Access CLK) ...................................................................................... 61 Figure 27. Read Cycle for Continuous Suspend................................... 61
Temporary Sector Unprotect ........................................................ 74
Figure 41. Temporary Sector Unprotect Timing Diagram..................... Figure 42. Sector/Sector Block Protect and Unprotect Timing Diagram.................................................................... Figure 43. Latency with Boundary Crossing ......................................... Figure 44. Latency with Boundary Crossing into Program/Erase Bank...................................................................... Figure 45. Example of Wait States Insertion ........................................ Figure 46. Back-to-Back Read/Write Cycle Timings............................. 74 75 76 77 78 79
SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 80
Read Cycle ................................................................................... 80
Figure 47. SRAM Read Cycle--Address Controlled ............................ 80 Figure 48. SRAM Read Cycle............................................................... 81
Write Cycle ................................................................................... 82
Figure 49. SRAM Write Cycle--WE# Control....................................... 82 Figure 50. SRAM Write Cycle--CE1#s Control.................................... 83 Figure 51. SRAM Write Cycle--UB#s and LB#s Control...................... 84
Erase and Programming Performance . . . . . . . BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Dimensions . . . . . . . . . . . . . . . . . . . . . .
85 85 85 86
Asynchronous Mode Read (VIO = 1.8 V) ......................................62
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 28. Asynchronous Mode Read with Latched Addresses ........... 63 Figure 29. Asynchronous Mode Read................................................... 63
TLB 089--89-ball Fine-Pitch Ball Grid Array (FBGA) 10 x 8 mm Package ............................................................................. 86
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 87
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ADVANCE
INFORMATION
PRODUCT SELECTOR GUIDE
Part Number Burst Frequency Speed Option Max Initial Synchronous Access Time, ns (TIACC) Reduced Wait-state Handshaking; Even Address Max Initial Synchronous Access Time, ns (TIACC) FLASH Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking Max Burst Access Time, ns (TBACC) Max Asynchronous Access Time, ns (TACC) Max CE# Access Time, ns (TCE) Max OE# Access Time, ns (TOE) SRAM Max Access time, ns (tACC) Max CE# Access time, ns (tCE) Max OE# Access, ns (tOE) 70 70 35 11 55 55 25 70 70 35 13.5 55 55 25 50 VCC, VIO = 1.65 - 1.95 V Am42BDS6408H 66 MHz 54 MHz
E8, E9 E3, E4 D8, D9 D3, D4 56 56 69 69
71 11
71
87.5
87.5 13.5
50
55
55
Note: Speed Options ending in "8" and "6" indicate the "reduced wait-state handshaking" option, which speeds initial synchronous accesses for even addresses. Speed Options ending in "9" and "7" indicate the "standard handshaking" option. See the AC Characteristics section of this datasheet for full specifications.
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INFORMATION
FLASH MEMORY BLOCK DIAGRAM
VCC VSS VSSIO VIO RDY Buffer RDY Erase Voltage Generator WE# RESET# WP# ACC State Control Command Register Input/Output Buffers DQ15-DQ0
PGM Voltage Generator Chip Enable Output Enable Logic Data Latch
CE# OE#
Y-Decoder Timer Address Latch VCC Detector
Y-Gating
X-Decoder
Cell Matrix
AVD# CLK
Burst State Control
Burst Address Counter
A21-A0
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INFORMATION
BLOCK DIAGRAM OF SIMULTANEOUS OPERATION CIRCUIT
VCC VSS VIO
Y-Decoder
Bank A Address
Latches and Control Logic
DQ15-DQ0
Bank A
A21-A0 X-Decoder OE#
Bank B Address
Latches and Control Logic
Y-Decoder
DQ15-DQ0
Bank B
WP# ACC RESET# WE# CE# AVD# RDY DQ15-DQ0
A21-A0
X-Decoder DQ15-DQ0 Status
STATE CONTROL & COMMAND REGISTER
A21-A0
Control
X-Decoder
Latches and Control Logic
Y-Decoder
Bank C Address
Bank C
DQ15-DQ0
A21-A0
A21-A0 X-Decoder
Bank D Address
Latches and Control Logic
Y-Decoder
Bank D
DQ15-DQ0
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INFORMATION
CONNECTION DIAGRAM
89-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1 NC B1 NC A2 ADV# B2 WP# C2 A3 D2 A2 E1 NC F1 NC E2 A1 F2 A0 G2 CE#f H2 CE1#s J2 NC K1 NC K2 NC A3 VSS B3 A7 C3 A6 D3 A5 E3 A4 F3 VSS G3 OE# H3 DQ0 J3 DQ8 K3 NC A4 CLK B4 LB# C4 UB# D4 A18 E4 A17 F4 DQ1 G4 DQ9 H4 DQ10 J4 DQ2 K4 VSS A5 NC B5 ACC C5 RESET# D5 RDY E5 NC F5 NC G5 DQ3 H5 VCCf J5 DQ11 K5 VIOf A6 NC B6 WE# C6 CE2s D6 A20 E6 NC F6 NC G6 DQ4 H6 VCCs J6 NC K6 NC A7 NC B7 A8 C7 A19 D7 A9 E7 A10 F7 DQ6 G7 DQ13 H7 DQ12 J7 DQ5 K7 NC A8 NC B8 A11 C8 A12 D8 A13 E8 A14 F8 NC G8 DQ15 H8 DQ7 J8 DQ14 K8 NC A9 NC B9 NC C9 A15 D9 A21 E9 NC F9 A16 G9 NC H9 VSS J9 NC K9 NC K10 NC E10 NC F10 NC A10 NC SRAM Only
Flash Only
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
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ADVANCE
INFORMATION High = device ignores address inputs WP# = Hardware write protect input. At VIL, disables program and erase functions in the two outermost sectors. Should be at VIH for all other conditions. = At VID, accelerates programming; automatically places device in unlock bypass mode. At VIL, locks all sectors. Should be at VIH for all other conditions.
PIN DESCRIPTION
A18-A0 A21-A19 DQ15-DQ0 CE#f CE1#s CE2s OE# WE# UB#s LB#s RESET# VCCf = 19 Address Inputs (Common) = 3 Address Inputs (Flash) = 16 Data Inputs/Outputs (Common) = Chip Enable (Flash) = Chip Enable 1 (SRAM) = Chip Enable 2 (SRAM) = Output Enable (Common) = Write Enable (Common) = Upper Byte Control (SRAM) = Lower Byte Control (SRAM) = Hardware Reset Pin, Active Low = Flash 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Input & Output Buffer Power Supply must be tied to VCC. = SRAM Power Supply = Output Buffer Ground = Device Ground (Common) = Pin Not Connected Internally = Ready output; indicates the status of the Burst read. Low = data not valid at expected time. High = data valid. = CLK is not required in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. = Address Valid input. Indicates to device that the valid address is present on the address inputs (A21-A0). Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched.
19
ACC
LOGIC SYMBOL
A18-A0
A21-A19 CE#f CE1#s CE2s OE# WE# WP# RESET# UB#s LB#s ACC AVD# CLK RDY DQ15-DQ0 16
VIOf VCCs VSSIOf VSS NC RDY
CLK
AVD#
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INFORMATION
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am42BDS6408 H D 8 I T
Tape and Reel
T S I 8 9 3 4 E D H
= = = = = = = = = =
7 Inches 13 Inches Industrial (-40C to +85C) Reduced wait-state handshaking Enabled + 70 ns SRAM Standard handshaking + 70 ns SRAM Reduced Wait-state handshaking Enabled + 55 ns SRAM Standard handshaking + 55 ns SRAM 66 MHz 54 MHz 0.13 um
TEMPERATURE RANGE
HANDSHAKING OPTIONS + SRAM speed
SPEED
PROCESS TECHNOLOGY
DEVICE NUMBER/DESCRIPTION
Am42BDS6408H 64 Megabit (4 M x 16-Bit) CMOS Flash Memory, Simultaneous Read/Write, Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase 8 Mb (512 K x 16-bit) SRAM WP# at VIL level protects top and bottom sectors
Valid Combinations
Valid Combinations Package Marking M420000070 66 Am42BDS6408HE9 Am42BDS6408HD8 Am42BDS6408HD9 I Am42BDS6408HE3 Am42BDS6408HE4 Am42BDS6408HD3 Am42BDS6408HD4 M420000074 66 M420000075 M420000071 70 M420000072 54 M420000073 Flash Burst Frequency (MHz) SRAM Speed (ns)
Order Number Am42BDS6408HE8
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Note: For the Am29BDS640H, the last digit of the speed grade specifies the VIO range of the device. Speed options ending in "8" and "9" (e.g., D8, D9) indicate a 1.8 Volt VIO range.
55
M420000076 54 M420000077
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INFORMATION
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1.
Device Bus Operations
CLK (See Note) X X X L L
Operation Asynchronous Read - Addresses Latched Asynchronous Read - Addresses Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle
CE# L L L L H X
OE# L L H H X X
WE# H H L L X X
A21-0 Addr In Addr In Addr In Addr In HIGH Z HIGH Z
DQ15-0 I/O I/O I/O I/O HIGH Z HIGH Z
RESET# H H H H H L
AVD#
X X
X X
L L H X L
X L X X X
H H H H H
Addr In HIGH Z HIGH Z HIGH Z HIGH Z
X Burst Data Out HIGH Z HIGH Z I/O
H H H L H X H X X
Legend: L = Logic 0, H = Logic 1, X = Don't Care, S = Stable Logic 0 or 1 but no transitions. Note: Default active edge of CLK is the rising edge.
VersatileIOTM (VIO) Control
The (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. VersatileIOTM
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t C E ) is the delay from the stable addresses and stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition.
Requirements for Asynchronous Read Operation (Non-Burst)
To read data from the memory array, the system must first assert a valid address on A21-A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15-DQ0. Since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. 12
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a preset length.
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INFORMATION If the clock frequency is less than 6 MHz during a burst mode operation, additional latencies will occur. RDY indicates the length of the latency by pulsing low. 8-, 16-, and 32-Word Linear Burst with Wrap Around The remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 2.) Table 2.
Mode 8-word 16-word 32-word
When the device first powers up, it is enabled for asynchronous read operation. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. See "Set Configuration Register Command Sequence" section on page 30 and "Command Definitions" section on page 30 for further details. Once the system has written the "Set Configuration Register" command sequence, the device is enabled for synchronous reads only. The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are output tBACC after the active edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003Fh. During the time the device is outputting data at this fixed internal address boundary (address 00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency occurs before data appears for the next address (address 000040h, 000080h, 0000C0h, etc.). The RDY output indicates this condition to the system by pulsing low. For standard handshaking devices, there is no two cycle latency between 3Fh and 40h (or offset from these values by a multiple of 64) if the latched address was 3Eh or 3Fh (or offset from these values by a multiple of 64). See Figure 43, "Latency with Boundary Crossing," on page 76. For reduced wait-state handshaking devices, if the address latched is 3Eh or 3Fh (or offset from these values by a multiple of 64) two additional cycle latency occurs prior to the initial access and the two cycle latency between 3Fh and 40h (or offset from these values by a multiple of 64) will not occur. The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 1, "Device Bus Operations," on page 12. If the host system crosses the bank boundary while reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as described above in the subsequent bank. If the host system crosses the bank boundary while the device is programming or erasing, the device will provide read status information. The clock will be ignored. After the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse. October 23, 2003
Burst Address Groups
Group Size Group Address Ranges 8 words 16 words 32 words 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,...
As an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38- 3F h, and the burs t s equenc e would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 64 words; thus, no wait states are inserted (except during the initial access). The RDY pin indicates when data is valid on the bus. The devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address).
Burst Suspend/Resume
The Burst Suspend/Resume feature allows the system to temporarily suspend a synchronous burst operation during the initial access (before data is available) or after the device is outputting data. When the burst operation is suspended, any previously latched internal data and the current state are retained. Burst Suspend requires CE# to be asserted, WE# de-asserted, and the initial address latched by AVD# or the CLK edge. Burst Suspend occurs when OE# is de-asserted. See Figure 18, "Reduced Wait-state Handshake Burst Suspend/Resume at an even address," on page 57, Figure 19, "Reduced Wait-state Handshake Burst Suspend/Resume at an odd address," on page 57, Figure 20, "Reduced Wait-state 13
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INFORMATION The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the "Autoselect Command Sequence" section for more information.
Handshake Burst Suspend/Resume at address 3Eh (or offset from 3Eh)," on page 58, Figure 21, "Reduced Wait-state Handshake Burst Suspend/Resume at address 3Fh (or offset from 3Fh by a multiple of 64)," on page 58, Figure 22, "Standard Handshake Burst Suspend prior to Initial Access," on page 59, Figure 23, "Standard Handshake Burst Suspend at or after Inital Access," on page 59, Figure 24, "Standard Handshake Burst Suspend at address 3Fh (starting address 3Dh or earlier)," on page 60, Figure 25, "Standard Handshake Burst Suspend at address 3Eh/3Fh (without a valid Initial Access)," on page 60, and Figure 26, "Standard Handshake Burst Suspend at address 3Eh/3Fh (with 1 Access CLK)," on page 61. Burst plus Burst Suspend should not last longer than tRCC without re-latching an address or crossing an address boundary. To resume the burst access, OE# must be re-asserted. The next active CLK edge will resume the burst sequence where it had been suspended. See, Figure 27, "Read Cycle for Continuous Suspend," on page 61. The RDY pin is only controlled by CE#. RDY will remain active and is not placed into a high-impedance state when OE# is de-asserted.
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the sa me bank (except the sector being erased). Figure 46, "Back-to-Back Read/Write Cycle Timings," on page 79 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Character i sti cs tabl e for read-while-program and read-while-erase current specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous write operation. While the device is configured in Asynchronous read it is able to perform Asynchronous write operations only. CLK is ignored in the Asynchronous programming mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and WE# address latch is supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to V IH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. The asynchronous and synchronous programing operation is independent of the Set Device Read Mode bit in the Configuration Register (see Table 15, "Configuration Register," on page 33). The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sectors, or the entire device. Table 10, "Sector Address Table," on page 26 indicates the address space that each sector occupies. The device address space is divided into four banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain both 4 Kword boot sectors in addition to 32 Kword sectors. A
Configuration Register
The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active.
Reduced Wait-state Handshaking Option
The device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. The presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. See "Autoselect Command Sequence" for details. For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. See "Set Configuration Register Command Sequence" section on page 30 section for more information. The device will automatically delay RDY and data by one additional clock cycle when the starting address is odd.
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INFORMATION mode and uses the higher voltage on the input to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC input returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VHH. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions.
"bank address" is the address bits required to uniquely select a bank. Similarly, a "sector address" is the address bits required to uniquely select a sector. ICC2 in the "DC Characteristics" section on page 49 represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass
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Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords
INFORMATION
Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
Sector SA135 SA136 SA137 SA138 SA139 SA140 SA141
A21-A12 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130 SA131 SA132 SA133 SA134
A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000
Sector/Sector Block Protection and Unprotection
The hardware sector protection feature disables both programming and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 3, " A m 4 2 B D S 6 4 0 8 H B o o t S e c t o r / S e c t o r B l o ck Addresses for Protection/Unprotection," on page 16 Sector Protection The Am42BDS6408H features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outermost sectors. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Selecting a Sector Protection Mode All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will permanently set the part to op-
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INFORMATION ity of the user to perfor m the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no ha r dwa r e m ech a ni sm t o p r eve n t se ct or P PBs over-erasure. Persistent Protection Bit Lock (PPB Lock) A global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is individually modifiable through the DYB Write Command. When the par ts are first shipped, the PPBs are cleared. The DYBs and PPB Lock are defaulted to power up in the cleared state - meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PBB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the
erate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Command Sequence" section on page 33 for details.
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: Persistently Locked--A sector is protected and cannot be changed. Dynamically Locked--The sector is protected and can be changed by a simple command Unlocked--The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of "bits" are going to be used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors ("Am42BDS6408H Boot Sector/Sector Block Addresses for Protection/Unprotection" section on page 16). All 4 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Program Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibil-
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INFORMATION In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a g i ve n s e c t o r c a n b e v e r i f i e d b y w r i t i n g a DYB/PPB/PPB lock verify command to the device.
PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP# write protect pin adds a final level of hardware protection to the four highest and four lowest 4 Kbyte sectors (SA0 - SA3, SA138 - SA141 for a dual boot). When this pin is low it is not possible to change the contents of these four sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. Note: to achieve the best protection, it's recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP# = VIL. Table 4. Sector Protection Schemes
PPB Lock 0 1 0 0 0 1 1 1 Protected--PPB not changeable, DYB is changeable Protected--PPB and DYB are changeable
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit is set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region of the flash memory. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-pro-
DYB 0 0 0 1 1 0 1 1
PPB 0 0 1 0 1 1 0 1
Sector State Unprotected--PPB and DYB are changeable Unprotected--PPB not changeable, DYB is changeable
Table 4 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector.
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INFORMATION Password Verify command from reading the contents of the password on the pins of the device.
grammed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 s delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password.
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1". If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode.
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first program the password. AMD recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (V ID ) to be placed on the RESET# pin. Refer to Figure 2, "In-System Sector Protection/ Sector Unprotection Algorithms," on page 21 for details on this procedure. Note that for sector unprotect, all unprotected sectors must be first protected prior to the first sector write cycle. Once the Password Mode Locking bit or Persistent Protection Locking bit are set, the high voltage sector protect/unprotect capability is disabled.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the "DC Characteristics" section on page 49 represents the standby current specification.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Program Command" section on page 37 and "Password Verify Command" section on page 37). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the
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INFORMATION Embedded Algorithms) before the device is ready to read data again. If RESET# is asser ted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after RESET# returns to VIH. Refer to the "AC Characteristics" section on page 64 for RESET# parameters and to Figure 30, "Reset Timings," on page 64 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. Figure 1. Temporary Sector Unprotect Operation
START
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the device automatically enables this mode when either the first active CLK level is greater than tACC or the CLK runs slower than 5 MHz. Note that a new burst operation is required to provide new data. ICC6 in the "DC Characteristics" section on page 49 represents the automatic sleep mode current specification. RESET#: Hardware Reset Input The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.2 V, the standby current will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the device requires a time of tREADY (during
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes: 1. All protected sectors unprotected (If WP# = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again.
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INFORMATION
START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 150 s Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 No
No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT = 1
Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 Set up next sector address
No No PLSCNT = 25? Yes Data = 01h?
Increment PLSCNT
Yes
No Yes No
Device failed
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes
Data = 00h? Yes
Device failed Write reset command
Last sector verified? Yes
No
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove VID from RESET#
Write reset command Sector Unprotect complete
Figure 2. In-System Sector Protection/ Sector Unprotection Algorithms October 23, 2003 Am42BDS6408H 21
ADVANCE
INFORMATION the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The Customer-lockable SecSi Sector area can be protected using one of the following procedures: Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. Write the three-cycle Enter SecSi Sector Secure Region command sequence, and then use the alternate method of sector protection described in the High Voltage Sector Protection section. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 16, "Command Definitions," on page 40 for command definitions). The device offers two types of data protection at the sector level: The PPB and DYB associated command sequences disables or re-enables both program and erase operations in any sector or sector group. When WP# is at VIL, the four outermost sectors are locked. When ACC is at VIL, all sectors are locked. The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
SecSiTM (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The SecSi sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. It uses in dica to r b its (DQ6 , D Q7) t o in dica te t he fa ctory-locked and customer-locked status of the part. The system accesses the SecSi Sector through a command sequence (see "Enter SecSiTM Sector/Exit SecSi Sector Command Sequence"). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Factory-Locked Area (64 words) T h e fa c t o r y - l o cke d a r e a o f t h e S e c S i S e c t o r (000000h-00003Fh) is locked when the par t is shipped, whether or not the area was programmed at the factory. The SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a "1". AMD offers the ExpressFlash service to program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only AMD can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact an AMD representative for details on using AMD's ExpressFlash service. Table 5. SecSiTM Sector Addresses
Sector Size Am42BDS6408H Factory-Locked Area Customer-Lockable Area 128 words 64 words 64 words
Address Range 000000h-00007Fh 000000h-00003Fh 000040h-00007Fh
Customer-Lockable Area (64 words) The customer-lockable area of the SecSi Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The SecSi Sector Customer-locked Indicator Bit (DQ6) is shipped as "0" and can be permanently locked to "1" by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that
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ADVANCE
INFORMATION CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the eight "outermost" 4 Kword boot sectors. If the system asserts VIH on the WP# pin, the device reverts to whether sectors 0-3 and 138-141 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in "PPB Program Command" section on page 38. Note that the WP# pin must not be left floating or unconnected; inconsistent behavior of the device may result. Low VCC Write Inhibit When V CC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 6-9. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 6-9. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the AMD site at the following URL: http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies
Table 6.
Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
CFI Query Identification String
Description
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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ADVANCE Table 7.
Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0017h 0019h 0000h 0000h 0004h 0000h 0009h 0000h 0004h 0000h 0004h 0000h
INFORMATION
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 8.
Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0017h 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 007Dh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description
Device Size =
2N
byte
Flash Device Interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
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INFORMATION
Table 9.
Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 000Ch
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0011 = 0.13 m
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh
0002h 0001h 0000h 0007h 0077h 0001h 0000h 00B5h
Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 07 = Advanced Sector Protection Simultaneous Operation Number of Sectors in all banks except boot block Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 01h = Dual Boot Device, 02h = Bottom Boot Device, 03h = Top Boot Device Program Suspend. 00h = not supported Bank Organization: X = Number of banks Bank A Region Information. X = Number of sectors in bank Bank B Region Information. X = Number of sectors in bank Bank C Region Information. X = Number of sectors in bank Bank D Region Information. X = Number of sectors in bank
4Eh
00C5h
4Fh 50h 57h 58h 59h 5Ah 5Bh
0001h 0000h 0004h 0017h 0030h 0030h 0017h
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ADVANCE Table 10.
Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Bank D SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 Bank C SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
INFORMATION Sector Address Table
Sector Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
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ADVANCE
Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 Bank C SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
INFORMATION
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Address Range 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
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ADVANCE
Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 Bank B SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102
INFORMATION
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh
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ADVANCE
Bank Sector SA103 SA104 SA105 SA106 SA107 SA108 SA109 Bank B SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank A SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
INFORMATION
Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords Address Range 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
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ADVANCE
INFORMATION
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 16, "Command Definitions," on p a g e 4 0 d e f i n e s t h e va li d r e g i s t e r co m m a n d sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. Refer to the AC Characteristics section for timing diagrams. be C0h, address bits A11-A0 should be 555h, and address bits A19-A12 set the code to be latched. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock).
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data from any non-erase-suspended sector within the same bank. See the "Erase Suspend/Erase Resume Commands" section on page 36 for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the "Reset Command" section on page 33 for more information. See also "Requirements for Asynchronous Read Operation (Non-Burst)" section on page 12 and "Requirements for Synchronous (Burst) Read Operation" section on page 12 for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figure 13, "CLK Synchronous Burst Mode Read (rising active CLK)," on page 54, Figure 15, "Synchronous Burst Mode Read," on page 55, and Figure 28, "Asynchronous Mode Read with Latched Addresses," on page 63 show the timings.
Power-up/ Hardware Reset
Asynchronous Read Mode Only
Set Burst Mode Configuration Register Command for Synchronous Mode (A19 = 0)
Set Burst Mode Configuration Register Command for Asynchronous Mode (A19 = 1)
Synchronous Read Mode Only
Figure 3.
Synchronous/Asynchronous State Diagram
Read Mode Setting On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. Address A19 determines this setting: "1" for asynchronous mode, "0" for synchronous mode. Programmable Wait State Configuration The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Address bits A14-A12 determine the setting (see Table 11, "Programmable Wait State Settings," on page 31). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency.
Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. The configuration register must be set before the device will enter burst mode. The configuration register is loaded with a three-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should
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ADVANCE Table 11.
A14 0 0 0 0 1 1 1 1
INFORMATION Table 12. Wait States for Reduced wait-state Handshaking
VIO = 1.8 V System Frequency Range 6-22 MHz 22-28 MHz 28-43 MHz 43-54 MHz 6-28 MHz 28-35 MHz 35-53 MHz 53-66 MHz Even Initial Address 2 2 3 4 2 2 3 4 Odd Initial Address 2 3 4 5 2 3 4 5 E (66 MHz) D (54 MHz) Device Speed Rating
Programmable Wait State Settings
A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 Total Initial Access Cycles 2 3 4 5 6 7 (default) Reserved Reserved
Notes: 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2.
VIO = 1.5 V
It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting. Reduced Wait-state Handshaking Option If the device is equipped with the reduced wait-state handshaking option, the host system should set address bits A14-A12 to 010 for the system/device to execute at maximum speed. Table 12 describes the typical number of clock cycles (wait states) for various conditions.
System Frequency Range 6-18 MHz 18-22 MHz 22-33 MHz 33-45 MHz 45-54 MHz 6-23 MHz 23-28 MHz 28-42 MHz 42-56 MHz 56-66 MHz
Even Initial Address 2 2 3 4 5 2 2 3 4 5
Odd Initial Address 2 3 4 5 6 2 3 4 5 6
Device Speed Rating
D (54 MHz)
E (66 MHz)
Notes: 1. If the latched address is 3Eh or 3Fh (or an address offset from either address by a multiple of 64), add two access cycles to the values listed. 2. In the 8-, 16-, and 32-word burst modes, the address pointer does not cross 64-word boundaries (3Fh, or addresses offset from 3Fh by a multiple of 64). 3. Typical initial access cycles may vary depending on system margin requirements.
Standard Handshaking Option For optimal burst mode performance on devices with the standard handshaking option, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency.
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ADVANCE
INFORMATION Table 14 shows the address bits and settings for the four read modes. Table 14. Read Mode Settings
Address Bits Burst Modes Continuous 8-word linear wrap around A16 0 0 1 1 A15 0 1 0 1
Table 13 describes the typical number of clock cycles (wait states) for various conditions with A14-A12 set to 101. Table 13. Wait States for Standard Handshaking
Typical No. of Clock Cycles after AVD# Low 7
Conditions at Address Initial address Initial address is 3E or 3Fh (or offset from these addresses by a multiple of 64) and is at boundary crossing*
7
16-word linear wrap around 32-word linear wrap around
* In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3Fh).
Note: Upon power-up or hardware reset the default setting is continuous.
Burst Active Clock Edge Configuration The autoselect function allows the host system to determine whether the flash device is enabled for h a nd sh a kin g . Se e t he " Au t o se le ct C om m an d Sequence" section on page 33 for more information. Read Mode Configuration The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. By default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. Subsequent outputs will also be on the following rising edges, barring any delays. The device can be set so that the falling clock edge is active for all synchronous accesses. Address bit A17 determines this setting; "1" for rising active, "0" for falling active. RDY Configuration By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting; "1" for RDY active with data, "0" for RDY active one clock cycle before valid data. In asynchronous mode, RDY is an open-drain output.
Configuration Register
Table 15 shows the address bits that determine the configuration register settings for various device functions.
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ADVANCE Table 15.
Address BIt A19 A18 A17 Function Set Device Read Mode RDY Clock Settings (Binary)
INFORMATION Configuration Register
0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) 0 = RDY active one clock cycle before data 1 = RDY active with data (default) 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK (default) Synchronous Mode
A16 A15
Read Mode
00 = Continuous (default) 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around
A14 A13 A12
000 = Data is valid on the 2th active CLK edge after AVD# transition to VIH 001 = Data is valid on the 3th active CLK edge after AVD# transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH Programmable 011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH Wait State 101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default) 110 = Reserved 111 = Reserved
Note:Device will be in the default state upon power-up or hardware reset.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 16, "Command Definitions," on page 40 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. No subsequent data will be made available if the autoselect data is read in synchronous mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. Read commands to other banks will return data from the array. The following table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address, and
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INFORMATION internally generated program pulses and verifies the programmed cell margin. Table 16, "Command Definitions," on page 40 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the "Write Operation Status" section on page 43 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to primarily program to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four cycles in length instead of six cycles. Table 16, "Command Definitions," on page 40 shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode.
SA represents the sector address. The device ID is read in three cycles.
Description Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Sector Protection Verification Address (BA) + 00h (BA) + 01h (BA) + 0Eh (BA) + 0Fh Read Data 0001h 227Eh 221Eh 2201h 0001 (locked), 0000 (unlocked) DQ15 - DQ8 = 0 DQ7: Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6: Customer Lock Bit Indicator Bits (BA) + 03h 1 = Locked, 0 = Not Locked DQ5: Handshake Bit 1 = Reduced Wait-state Handshake, 0 = Standard Handshake
(SA) + 02h
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).
Enter SecSiTM Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 16, "Command Definitions," on page 40 shows the address and data requirements for both command sequences.
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides
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INFORMATION trols or timings during these operations. Table 16, "Command Definitions," on page 40 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the "Write Operation Status" section on page 43 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. The command sequence is two cycles cycles in length instead of six cycles. See Table 16, "Command Definitions," on page 40 for details on the unlock bypass command sequences. Figure 5, "Erase Operation," on page 37 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters and timing diagrams.
The device offers accelerated program operations through the ACC input. When the system asserts VHH on this input, the device automatically enters the Unlock Bypass mode. The system may then write the t wo - c y c le U n l o ck B y p a s s p ro gra m c o m m a n d sequence. The device uses the higher voltage on the ACC input to accelerate the operation. Figure 4, "Program Operation," on page 35 illustrates the algorithm for the program operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters, and Figure 31, "Asynchronous Program Operation Timings: AVD# Latched Addresses," on page 66 and Figure 33, "Synchronous Program Operation Timings: WE# Latched Addresses," on page 68 for timing diagrams.
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 16, "Command Definitions," on page 40 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted.
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 16 for program command sequence.
Figure 4.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any con-
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INFORMATION this command. This command is valid only during the sector erase operation, including the minimum 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Figure , "Write Operation Status," on page 43 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to the "Write Operation Status" section on page 43 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the " A m 4 2 B D S 6 4 0 8 H B o o t S e c t o r / S e c t o r B l o ck Addresses for Protection/Unprotection" section on page 16 and "Autoselect Command Sequence" section on page 33 for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command
The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See "DQ3: Sector Erase Timer" section on page 46.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to the "Write Operation Status" section on page 43 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. Figure 5, "Erase Operation," on page 37 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the Figure , "AC Characteristics," on page 65 for parameters and timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing
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INFORMATION from the factory. All 64-bit password combinations are valid as a password.
are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Password Verify Command
START
Write Erase Command Sequence
The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F's onto the DQ data bus. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation.
Data Poll from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. When the Password Protection Mode Locking Bit is undergoing programming, Simultaneous Operation is disabled. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command.
Notes: 1. See Table 16 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 5.
Erase Operation
Password Program Command
The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. 4 Password Program commands are required to program the password. The user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program AlgorithmTM with the cell remaining as a "0". The password is all F's when shipped
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. When the Persistent Sector Protection Mode Locking Bit is undergoing programming, Simultaneous Operation is disabled.
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INFORMATION Password Unlock command 4 times. A1 and A0 are used for matching. Writing the Password Unlock command is not address order specific. The lower address A1-A0= 00, the next Password Unlock command is to A1-A0= 01, then to A1-A0= 10, and finally to A1-A0= 11. Once the Password Unlock command is entered for all four words, the RDY pin goes LOW indicating that the device is busy. Approximately 1uSec is required for each portion of the unlock. Once the first portion of the password unlock completes (RDY is not driven and DQ6 does not toggle when read), the Password Unlock command is issued again, only this time with the next part of the password. Four Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RDY signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock commands, the order, and when to read the PPB Lock bit to confirm successful password unlock. In order to relock the device into the Password Mode, the PPB Lock Bit Set command can be re-issued.
SecSi Sector Protection Bit Program Command
The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which prevents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the VCC -level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command, only while in the Persistent Sector Protection Mode.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A21-A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. The PPB Program command does not follow the Embedded Program algorithm.
DYB Write Command
The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (A21-A12) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. Exiting the DYB Write command is accomplished by writing the Read/Reset command.
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the 38
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased withOctober 23, 2003
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INFORMATION bit, removing power or resetting the device will clear the DYBs.
out margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
PPB Status Command
The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device.
PPB Lock Bit Status Command
The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device.
DYB Write Command
The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at hardware reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile
DYB Status Command
The programming of the DYB for a given sector can be verified by writing a DYB Status command to the device.
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INFORMATION
Command Definitions
Table 16.
Cycles First
Command Definitions
Bus Cycles (Notes 1-6) Third Fourth Data Fifth Sixth Seventh
Command Sequence (Note 1) Asynchronous Read (Note 7) Reset (Note 8) Manufacturer ID Autoselect (Note 9) Device ID Sector Lock Verify (Note 10) Indicator Bits (Note 11) Program Chip Erase Sector Erase Erase Suspend (Note 14) Erase Resume (Note 15) Set Configuration Register (Note 16) CFI Query (Note 17)
Unlock Bypass Entry Unlock Bypass Program (Notes 12, 13) Unlock Bypass Mode Unlock Bypass Sector Erase (Notes 12, 13) Unlock Bypass Erase (Notes 12, 13) Unlock Bypass CFI (Notes 12, 13) Unlock Bypass Reset
Second
Addr Data Addr Data Addr Data Addr RA XXX 555 555 555 555 555 555 555 BA BA 555 55
555 XX XX XX XX XX
Addr Data Addr Data Addr Data
1 1 4 6 4 4 4 6 6 1 1 3 1
3 2 2 2 1 2
RD F0 AA AA AA AA AA AA AA B0 30 AA 98
AA A0 80 80 98 90 XXX 00 2AA PA SA XXX 55 PD 30 10 555 20
2AA 2AA 2AA 2AA 2AA 2AA 2AA
55 55 55 55 55 55 55
(BA) 555 (BA) 555 (SA) 555 (BA) 555 555 555 555
90 90 90 90 A0 80 80
(BA) X00 (BA) X01 (SA) X02 (BA) X03 PA 555 555
0001 227E (Note 10) (Note 11) Data AA AA 2AA 2AA 55 55 555 SA 10 30 (BA) (BA) 221E 2201 X0E X0F
2AA
55
(CR) 555
C0
Sector Protection Command Definitions SecSi Sector Entry SecSi Sector SecSi Sector Exit SecSi Protection Bit Program (Notes 18, 19, 21) 3 4 6 555 555 555 AA AA AA 2AA 2AA 2AA 55 55 55 555 555 555 88 90 60 XX (SA) OW XX0 Password Program (Notes 18, 23) 4 555 AA 2AA 55 555 38 XX1 XX2 XX3 Password Protection Password Verify 4 555 AA 2AA 55 555 C8 XX0 XX1 XX2 XX3 Password Unlock (Note 23) 7 555 AA 2AA 55 555 28 XX0 00 68 PD0 PD1 PD2 PD3 PD0 PD1 PD2 PD3 PD0 XX1 PD1 XX2 PD2 XX3 PD3 (SA) OW 48 OW RD (0)
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Cycles
INFORMATION
Bus Cycles (Notes 1-6)
Command Sequence (Note 1)
PPB Program (Notes 18, 19, 21) PPB Command s All PPB Erase (Notes 18, 19, 22, 24) PPB Status (Note 25) PPB Lock Bit Set PPB Lock Bit PPB Lock Bit Status (Note 19) DYB Write DYB DYB Erase DYB Status Password Protection Mode Locking Bit Program (Notes 18, 19, 21) Persistent Protection Mode Locking Bit Program (Notes 18, 19, 21) Password Protection Mode Locking Bit Read (Notes 18, 19, 21) Persistent Protection Mode Locking Bit Read (Notes 18, 19, 21)
First
Second
Third
Fourth Data
68 60 RD (0)
Fifth
Sixth
Seventh
Addr Data Addr Data Addr Data Addr
555 555 555 555 555 555 555 555 555 555 555 555 AA AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 555 555 (BA) 555 555 (BA) 555 555 555 (BA) 555 555 555 555 555 60 60 90 78 58 48 48 58 60 60 60 60 SA SA SA SA PL SL PL SL (SA) + WP WP (SA) X02
Addr Data Addr Data Addr Data
(SA) + WP WP 48 40 XX XX RD (0) RD (0)
6 6 4 3 4 4 4 4 6 6 4 4
RD (1) X1 X0 RD (0) 68 68 RD (0) RD (0) PL SL 48 48 PL SL RD (0) RD (0)
Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21-A12 uniquely select any sector. BA = Address of the bank (A21, A20, A19) that is being switched to autoselect mode, is in bypass mode, or is being erased. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. CR = Configuration Register address bits A19-A12.
OW = Address (A7-A0) is (00011010). PD3-PD0 = Password Data. PD3-PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. PL = Address (A7-A0) is (00001010) RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0. RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0. SL = Address (A7-A0) is (00010010) WD= Write Data. See "Configuration Register" definition for specific write data WP = Address (A7-A0) is (00000010)
Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PD3-PD0. 5. Unless otherwise noted, address bits A21-A12 are don't cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase 9.
Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect Command Sequence section for more information.
10. The data is 0000h for an unlocked sector and 0001h for a locked sector 11. DQ15 - DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 = Not Locked), DQ6: Customer Lock Bit (1 = Locked, 0 = Not Locked), DQ5: Handshake Bit (1 = Reduced wait-state Handshake, 0 = Standard Handshake), DQ4 - DQ0 = 0 12. The Unlock Bypass command sequence is required prior to this command sequence. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
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INFORMATION
21. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 22. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 23. The entire four bus-cycle sequence must be entered for each portion of the password. 24. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 25. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set.
14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. See "Set Configuration Register Command Sequence" for details. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. 18. The Reset command returns the device to reading the array. 19. Regardless of CLK and AVD# interaction or Control Register bit 15 setting, command mode verifies are always asynchronous read operations. 20. ACC must be at VHH during the entire operation of this command
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INFORMATION
WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 18, "Write Operation Status," on page 47 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress. invalid. Valid data on DQ7-DQ0 will appear on successive read cycles. Table 18, "Write Operation Status," on page 47 shows the outputs for Data# Polling on DQ7. Figure 6, "Data# Polling Algorithm," on page 43 shows the Data# Polling al g or it h m. F ig u r e 37 , " D a t a # Po l lin g T i m in g s (During Embedded Algorithm)," on page 72 in the AC Characteristics section shows the Data# Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming dur ing Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still
START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 6.
Data# Polling Algorithm
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INFORMATION cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 ms after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 7, "Toggle Bit Algorithm," on page 45, "DQ6: Toggle Bit I" o n p a g e 4 4 , F i g u r e 3 8 , " To g g l e B i t T i m i n g s (During Embedded Algorithm)," on page 72 (toggle bit timing diagram), and Table 17, "DQ6 and DQ2 Indications," on page 46. Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state.
RDY: Ready
The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. The following conditions cause the RDY output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3Fh. When the device is configured in Asynchronous Mode, the RDY is an open-drain output pin which indicates whether an Embedded Algorithm is in progress or completed. The RDY status is valid after the rising edge of the final WE# pulse in the command sequence. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is in high impedance (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 18, "Write Operation Status," on page 47 shows the outputs for RDY.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address
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INFORMATION DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 17, "DQ6 and DQ2 Indications," on page 46 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 7, "Toggle Bit Algorithm," on page 45, "DQ6: Toggle Bit I" o n p a g e 4 4 , F i g u r e 3 8 , " To g g l e B i t T i m i n g s (During Embedded Algorithm)," on page 72, and Table 17, "DQ6 and DQ2 Indications," on page 46.
START
Read Byte (DQ7-DQ0) Address = VA Read Byte (DQ7-DQ0) Address = VA
DQ6 = Toggle? Yes
No
No
DQ5 = 1?
Yes Read Byte Twice (DQ7-DQ0) Adrdess = VA
DQ6 = Toggle?
No
Yes FAIL PASS
Note:The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information.
Figure 7.
Toggle Bit Algorithm
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.
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If device is programming, and the system reads at any address, at an address within a sector selected for erasure, actively erasing, at an address within sectors not selected for erasure, at an address within a sector selected for erasure, erase suspended, at an address within sectors not selected for erasure, programming in erase suspend at any address,
INFORMATION
DQ6 and DQ2 Indications
then DQ6 toggles, toggles, toggles, does not toggle, returns array data, toggles, and DQ2 does not toggle. also toggles. does not toggle. toggles. returns array data. The system can read from any sector not selected for erasure. is not applicable.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7, "Toggle Bit Algorithm," on page 45 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (Figure 7, "Toggle Bit Algorithm," on page 45).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also "Sector Erase Command Sequence" on page 35. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the
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INFORMATION mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 18 shows the status of DQ3 relative to the other status bits.
device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase com-
Table 18.
Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Erase Suspended Sector Non-Erase Suspended Sector
Write Operation Status
DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RDY (Note 5) 0 0 High Impedance High Impedance 0
Erase Suspend Mode
Erase-SuspendRead (Note 4)
Erase-Suspend-Program
Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. 4. The system may read either asynchronously or synchronously (burst) while in erase suspend. 5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This is available in the Asynchronous mode only.
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INFORMATION
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) . . . . . . . -0.5 V to VIO + 0.5 V VCC (Note 1) . . . . . . . . . . . . . . . . . . -0.5 V to +2.5 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +2.5 V A9, RESET#, ACC (Note 1) . . . . . -0.5 V to +12.5 V Output Short Circuit Current (Note 3) . . . . . . 100 mA
Notes: 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 9. 2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 3. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns 20 ns 20 ns +0.8 V -0.5 V -2.0 V 20 ns
Figure 8. Maximum Negative Overshoot Waveform
20 ns
Figure 9. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Supply Voltages VCC Supply Voltages . . . . . . . . . . .+1.65 V to +1.95 V . . . . . . . . . . . . . . . . . . . . . . . . . . VCC >= VIO - 100mV VIO Supply Voltages: . . . . . . . . . . +1.65 V to +1.95 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
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INFORMATION
DC CHARACTERISTICS CMOS COMPATIBLE
Parameter Description ILI ILO Input Load Current Output Leakage Current Test Conditions Note: 1 & 2 VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax CE# = VIL, OE# = VIH, WE# = VIH, burst length =8 CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous 54 MHz 9 Min Typ Max 1 1 17 Unit A A mA
54 MHz
8
15.5
mA
ICCB
VCC Active burst Read Current
54 MHz
7
14
mA
CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8 IIO1 VIO Non-active Output VCC Active Asynchronous Read Current (Note 3) VCC Active Write Current (Note 4) VCC Standby Current (Note 5) VCC Reset Current VCC Active Current (Read While Write) VCC Sleep Current Accelerated Program Current (Note 6) Input Low Voltage OE# = VIH 10 MHz ICC1 CE# = VIL, OE# = VIH, WE# = VIH 5 MHz 1 MHz ICC2 ICC3 ICC4 ICC5 ICC6 IACC CE# = VIL, OE# = VIH, ACC = VIH CE# = RESET# = VCC 0.2 V RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH, VACC = 12.0 0.5 V VIO = 1.8 V VIO = 1.5 V Input High Voltage Output Low Voltage Output High Voltage Voltage for Autoselect and Temporary Sector Unprotect Voltage for Accelerated Program Low VCC Lock-out Voltage VIO = 1.8 V VIO = 1.5 V IOL = 100 A, VIO = VCC = VCC min IOH = -100 A, VIO = VCC = VCC min VCC = 1.8 VIO - 0.1 11.5 11.5 1.0 VACC VCC -0.4 TBD VIO - 0.4 TBD
50 0.2 TBD 12 3.5 15 1 1 25 1 7 5
200 10 TBD 16 5 40 40 40 60 40 15 10 0.4 TBD VIO + 0.4 TBD 0.1
A A mA mA mA mA A A mA A mA mA V
VIL
VIH VOL VOH VID VHH VLKO
V V V
12.5 12.5 1.4
V V V
Note: 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. VIO= VCC 3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal to ICC3. 6. Total current during accelerated programming is the sum of VACC and VCC currents.
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INFORMATION
SRAM DC AND OPERATING CHARACTERISTICS
Parameter Symbol ILI ILO ICC Parameter Description Input Leakage Current Output Leakage Current Operating Power Supply Current Test Conditions VIN = VSS to VCC CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC IIO = 0 mA, CE1#s = VIL, CE2s = WE# = VIH, VIN = VIH or VIL Cycle time = 1 s, 100% duty, IIO = 0 mA, CE1#s 0.2 V, CE2 VCC - 0.2 V, VIN 0.2 V or VIN VCC - 0.2 V Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH IOL = 0.1 mA IOH = -0.1 mA CE1#s VCC - 0.2 V, CE2 VCC - 0.2 V (CE1#s controlled) or CE2 0.2 V (CE2s controlled), CIOs = VSS or VCC, Other input = 0 ~ VCC -0.2 (Note 2) 1.4 1.4 Min -1.0 -1.0 Typ Max 1.0 1.0 5 Unit A A mA
ICC1s
Average Operating Current
1
5
mA
ICC2s VOL VOH
Average Operating Current Output Low Voltage Output High Voltage
8
15 0.2
mA V V
ISB1
Standby Current (CMOS)
2
25
A
VIL
Input Low Voltage
0.4 VCC+0. 2 (Note 3)
V
VIH
Input High Voltage
V
Notes: 1. Typical values measured at VCC = 2.0 V, TA = 25C. Not 100% tested. 2. Undershoot is -1.0 V when pulse width 20 ns. 3. Overshoot is VCC + 1.0 V when pulse width 20 ns. 4. Overshoot and undershoot are sampled, not 100% tested.
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INFORMATION
TEST CONDITIONS
Table 19.
Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times CL Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Specifications
All Speed Options 30 5 0.0-VIO VIO/2 VIO/2 Unit pF ns V V V
Device Under Test
Figure 10.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
SWITCHING WAVEFORMS
VIO 0.0 V
All Inputs and Outputs
Input
VIO/2
Measurement Level
VIO/2
Output
Figure 11.
Input Waveforms and Measurement Levels
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INFORMATION
AC CHARACTERISTICS VCC Power-up
Parameter tVCS tVIOS tRSTH Description VCC Setup Time VIO Setup Time RESET# Low Hold Time Test Setup Min Min Min Speed 50 50 50 Unit s s s
tVCS
VCC tVIOS
VIO tRSTH
RESET#
Figure 12.
VCC Power-up Diagram
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INFORMATION
Synchronous/Burst Read (VIO = 1.8 V)
Parameter JEDEC Standard Description tIACC tIACC tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRDYS tRACC tAAS tAAH tCAS tAVC tAVD tACC tCKA tCKZ tOES tRCC Latency (Even address in Reduced wait-state Handshake mode) Latency (Standard Handshake or Odd address in Reduced wait-state Handshake mode Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note 1) Address Hold Time from CLK (Note 1) Data Hold Time from Next Clock Cycle Chip Enable to RDY Valid Output Enable to Output Valid Chip Enable to High Z Output Enable to High Z CE# Setup Time to CLK RDY Setup Time to CLK Ready Access Time from CLK Address Setup Time to AVD# (Note 1) Address Hold Time to AVD# (Note 1) CE# Setup Time to AVD# AVD# Low to CLK AVD# Pulse Access Time CLK to access resume CLK to High Z Output Enable Setup Time Read cycle for continuous suspend Max Max Max Min Min Min Max Max Max Max Min Min Max Min Min Min Min Min Max Max Max Min Max 4 10 50 11 8 4 1 E6, E7, E8, E9 (66 MHz) 56 71 11 4 6 3 11 11 8 8 4 4 11 4 6 0 5 12 55 13.5 10 5 D6, D7, D8, D9 (54 MHz) 69 87.5 13.5 5 7 4 13.5 13.5 10 10 5 5 13.5 5 7
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Notes: 1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. 2. Please contact AMD for availability of VIO = 1.5 V devices.
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INFORMATION
AC CHARACTERISTICS
CE# CLK tAVC AVD# tACS Addresses
Aa
tCES 1 2 3
7 cycles for initial access shown.
tCEZ 6 7
4
5
tAVD tBDH tBACC
Hi-Z
tACH Data tIACC tACC OE# tCR RDY
Hi-Z Da Da + 1
Da + n
tOEZ tRACC
Hi-Z
tOE
tRDYS
Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode.
Figure 13.
CE# CLK tAVC AVD# tACS Addresses
Aa
CLK Synchronous Burst Mode Read (rising active CLK)
tCES
4 cycles for initial access shown.
tCEZ 5
1
2
3
4
tAVD tBDH tBACC
Hi-Z
tACH Data tIACC tACC OE#
Hi-Z Da
Da + 1
Da + n
tOEZ tRACC
Hi-Z
tCR
tOE
RDY tRDYS
Notes: 1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode.
Figure 14.
CLK Synchronous Burst Mode Read (Falling Active Clock)
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INFORMATION
AC CHARACTERISTICS
tCAS CE# 1 CLK tAVC AVD# tAAS Addresses
Aa 7 cycles for initial access shown.
tCEZ 5 6 7
2
3
4
tAVD tBDH tBACC
Hi-Z
tAAH Data tIACC tACC OE# tCR RDY
Hi-Z Da Da + 1
Da + n
tOEZ tRACC
Hi-Z
tOE
tRDYS
Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode.
Figure 15.
Synchronous Burst Mode Read
tCES CE# 1 CLK tAVC AVD# tACS Addresses
A6
7 cycles for initial access shown.
2
3
4
5
6
7
tAVD tBDH tBACC tIACC tACC
tACH Data
D6 D7
D0
D1
D5
D6
OE# tCR RDY
Hi-Z
tOE
tRACC
tRDYS
Note: Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0-D7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in range (A6). See "Requirements for Synchronous (Burst) Read Operation". The Set Configuration Register command sequence has been written with A18=1; device will output RDY with valid data.
Figure 16.
8-word Linear Burst with Wrap Around
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INFORMATION
AC CHARACTERISTICS
tCES CE# 1 CLK tAVC AVD# tACS Addresses
Aa 6 wait cycles for initial access shown.
tCEZ 6
2
3
4
5
tAVD tBDH tBACC
Hi-Z
tACH Data tIACC tACC OE# tCR RDY
Hi-Z D0 D1
D2
D3
Da + n
tRACC tOE
tOEZ
Hi-Z
tRDYS
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle before valid data.
Figure 17.
Linear Burst with RDY Set One Cycle Before Data
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INFORMATION
AC CHARACTERISTICS
Suspend
Resume
x
x+1
x+2
x+3
x+4
x+5
x+6
x+7
x+8
CLK AVD# Addresses
tCKZ tCKA tOES tOES
OE# Data RDY
tRACC D(20)
D(20)
D(21)
D(22)
D(23)
D(23)
D(23)
D(24)
tRACC
Note: Figure is for any even address other than 3Eh (or multiple thereof).
Figure 18.
Reduced Wait-state Handshake Burst Suspend/Resume at an even address
Suspend
Resume
x
x+1
x+2
x+3
x+4
x+5
x+6
x+7
x+8
CLK AVD# Addresses
tCKZ tCKA tOES tOES
OE# Data RDY
D(23)
D(23)
D(24)
D(25)
D(25)
D(25)
D(26)
D(27)
tRACC
tRACC
Note: Figure is for any odd address other than 3Fh (or multiple thereof).
Figure 19.
Reduced Wait-state Handshake Burst Suspend/Resume at an odd address
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INFORMATION
AC CHARACTERISTICS
Suspend Resume
x
x+1
x+2
x+3
x+4
x+5
x+6
x+7
x+8
x+9
x+10
CLK AVD#
tOES
Addresses
tOES
OE#
tCKZ
tCKA
Data RDY
D(3E)
D(3E)
D(3F)
D(3F)
D(3F)
D(40)
D(41)
D(41)
D(41)
D(41) D(42)
tRACC
tRACC
Figure 20.
Reduced Wait-state Handshake Burst Suspend/Resume at address 3Eh (or offset from 3Eh)
Suspend
Resume
x
x+1
x+2
x+3
x+4
x+5
x+6
x+7
x+8
x+9
x+10
CLK AVD#
tOES
Addresses
tOES
OE#
tCKZ
tCKA
Data RDY
tRACC
D(3F)
D(3F)
D(3F)
D(3F)
D(40)
D(41)
D(41)
D(41)
D(42)
D(41) D(43)
tRACC tRACC
Figure 21.
Reduced Wait-state Handshake Burst Suspend/Resume at address 3Fh (or offset from 3Fh by a multiple of 64)
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INFORMATION
AC CHARACTERISTICS
Suspend Resume
CLK AVD#
1
2
3
4
5
6
7
x
x+1
x+2
x+3
x+4
x+5
x+6
x+7
x+8
tOES
tOES
Addresses OE# Data(1) RDY(1)
A(n) tCKA
D(n) tACC tRACC
D(n+1)
D(n+2)
3F
3F
D(3F)
D(40)
Data(2) RDY(2)
D(n)
D(n+1)
D(n+2)
D(n+3)
D(n+4)
D(n+5)
D(n+6)
tRACC
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) RDY goes low during the two-cycle latency during a boundary crossing. 2) RDY stays high when a burst sequence crosses no boundaries.
Figure 22.
Standard Handshake Burst Suspend prior to Initial Access
Suspend
Resume
CLK AVD#
1
2
3
4
5
6
7
8
9
x
x+1
x+2
x+3
tOES
tOES
tOES
Addresses OE#(1) Data(1)
A(n) tCKA tCKZ D(n) tACC tRACC tRACC tCKA
D(n)
D(n+1)
RDY(1) OE#(2) Data(2) RDY(2)
tRACC
D(n) tRACC
D(n+1) tRACC tRACC
D(n+1)
D(n+2)
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Burst suspend during the initial synchronous access 2) Burst suspend after one clock cycle following the initial synchronous access
Figure 23.
Standard Handshake Burst Suspend at or after Inital Access
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INFORMATION
AC CHARACTERISTICS
Suspend Resume
CLK AVD#
1
2
3
4
5
6
7
8
9
x
x+1
x+2
x+3
x+4
x+5
tOES
tOES
tOES
Addresses OE# Data
A(3D)
tCKA
tCKA tCKZ D(3F)
D(3D) tACC
D(3E)
D(3F)
D(3F) tRACC
D(3F)
D(4D)
RDY
tRACC
tRACC
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data.
Figure 24.
Standard Handshake Burst Suspend at address 3Fh (starting address 3Dh or earlier)
Suspend
Resume
CLK
1
2
3
4
5
6
7
8
x
x+1
x+2
x+3
x+4
x+5
x+6
AVD# Addresses(1) OE# Data(1)
tACC A(3E) tOES
tOES
tOES
tCKA tCKZ D(3E) tRACC tRACC D(3E) D(3F) D(40) D(41) D(42)
RDY(1) Addresses(2) Data(2)
A(3F)
tRACC
D(3F) tRACC
D(3F)
D(40)
D(41)
D(42)
D(43)
RDY(2)
tRACC
tRACC
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Address is 3Eh or offset by a multiple of 64 (40h) 2) Address is 3Fh or offset by a multiple of 64 (40h)
Figure 25.
Standard Handshake Burst Suspend at address 3Eh/3Fh (without a valid Initial Access)
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INFORMATION
AC CHARACTERISTICS
Suspend Resume
CLK AVD#
1
2
3
4
5
6
7
8
9
x
x+1
x+2
x+3
x+4
x+5
x+6
tOES
tOES
Addresses(1) OE# Data(1) RDY(1) (Even) Addresses(2) Data(2) RDY(2) (Odd)
A(3E) tOES tCKZ tACC D(3E) tRACC D(3F) tRACC D(3F) tRACC D(40) D(41) D(42) tCKA
A(3F)
D(3F) tRACC
D(40) tRACC
D(40)
D(41)
D(42)
D(43)
tRACC
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Address 3Eh or offset by a multiple of 64 (40h) 2) Address is 3Fh or offset by a multiple of 64 (40h)
Figure 26.
Standard Handshake Burst Suspend at address 3Eh/3Fh (with 1 Access CLK)
Suspend
Resume
CLK AVD#
1
2
3
4
5
6
7
x
x+1
x+2
x+3
x+4
x+5
tRCC
x+6
x+7
x+8
tOES
tOES
Addresses OE# Data(1) RDY
A(n) tCKA
D(n) tACC tRACC
D(n+1)
D(n+2)
D(3F)
D(3F)
D(3F)
D(40)
Data(2) CE#
D(n)
??? tRCC
???
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Device crosses a page boundary prior to tRCC 2) Device neither crosses a page boundary nor latches a new address prior to tRCC
Figure 27.
Read Cycle for Continuous Suspend
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INFORMATION
AC CHARACTERISTICS Asynchronous Mode Read (VIO = 1.8 V)
Parameter JEDEC Standard Description tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS Access Time from CE# Low Asynchronous Access Time (Note 1) AVD# Low Time Address Setup Time to Rising Edge of AVD Address Hold Time from Rising Edge of AVD Output Enable to Output Valid Read Output Enable Hold Time Toggle and Data# Polling Max Max Min Min Min Max Min Min Max Min 8 8 0 E3, E4, E8, E9 (66 MHz) 50 50 10 4 6 11 0 10 10 D6, D7, D8, D9 (54 MHz) TBD TBD 12 5 7 13.5
Unit ns ns ns ns ns ns ns ns ns ns
Output Enable to High Z (Note 2) CE# Setup Time to AVD#
Notes: 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested.
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INFORMATION
AC CHARACTERISTICS
CE# tOE tOEH WE# Data tACC Addresses tCAS AVD# tAVDP tAAVDS RA tAAVDH tCE Valid RD tOEZ
OE#
Note: RA = Read Address, RD = Read Data.
Figure 28.
Asynchronous Mode Read with Latched Addresses
CE# tOE tOEH WE# Data tACC Addresses RA tCE Valid RD tOEZ
OE#
AVD#
Note: RA = Read Address, RD = Read Data.
Figure 29.
Asynchronous Mode Read
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INFORMATION
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tReady tReady tRP tRH tRPD Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode Max Max Min Min Min All Speed Options 20 500 500 200 20 Unit s ns ns ns s
Note: Not 100% tested.
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
CE#, OE# tReady RESET# tRP
Figure 30.
Reset Timings
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INFORMATION
AC CHARACTERISTICS Erase/Program Operations (VIO = 1.8 V)
Parameter JEDEC Standard Description tAVAV tAVWL tWC tAS Write Cycle Time (Note 1) Address Setup Time (Notes 2, 3) Address Hold Time (Notes 2, 3) AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 4) Accelerated Programming Operation (Note 4) Sector Erase Operation (Notes 4, 5) tWHWH2 tWHWH2 tVID tVIDS tVCS tELWL tCS tAVSW tAVHW tACS tACH tAVHC tCSW Typ Chip Erase Operation (Notes 4, 5) VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) VCC Setup Time CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# Address Setup Time to CLK (Notes 2, 3) Address Hold Time to CLK (Notes 2, 3) AVD# Hold Time to CLK Clock Setup Time to WE# Min Min Min Min Min Min Min Min Min Min 4 4 4 6 4 5 54 500 1 50 0 5 5 5 7 5 ns s s ns ns ns ns ns ns ns Synchronous Min Asynchronous Synchronous Min Asynchronous Min Min Min Min Min Min Min Min Min Typ Typ 20 20 0 9 4 0.4 sec 20 10 20 0 0 0 0 30 20 20 12 45 ns ns ns ns ns ns ns ns ns s s 6 0 7 ns Min E6, E7, E8, E9 (66 MHz) 50 4 D6, D7, D8, D9 (54 MHz) 55 5 ns
Unit ns
tWLAX
tAH tAVDP
tDVWH tWHDX tGHWL
tDS tDH tGHWL tCAS
tWHEH tWLWH tWHWL
tCH tWP tWPH tSR/W
tWHWH1 tWHWH1
tWHWH1 tWHWH1
Notes:
1. Not 100% tested. 2. Asynchronous mode allows the Asynchronous program operation only. Synchronous mode allows both Asynchronous and Synchronous program operation. 3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In synchronous program operation timing, addresses are latched on the first of either the falling edge of WE# or the active edge of CLK. 4. See the "Erase and Programming Performance" section for more information. 5. Does not include the preprogramming time.
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INFORMATION
AC CHARACTERISTICS
VIH
Program Command Sequence (last two cycles)
Read Status Data
CLK
VIL
tAVDP AVD# tAS Addresses 555h tAH PA VA
In Progress
VA
Data
A0h
PD tDS tDH
Complete
CE#
OE# tWP WE# tCS
tCH
tWHWH1 tWPH tWC
tVCS VCC
Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A21-A12 are don't care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 31.
Asynchronous Program Operation Timings: AVD# Latched Addresses
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INFORMATION
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data
VIH
CLK
VIL
tAVSW tAVHW AVD# tAS tAH Addresses 555h PA VA
In Progress
tAVDP
VA
Data
A0h tDS tDH
PD
Complete
CE#
OE# tWP WE#
tCH
tWHWH1 tCS tWC tVCS VCC tWPH
Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A21-A12 are don't care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 32.
Asynchronous Program Operation Timings: WE# Latched Addresses
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INFORMATION
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tAVCH CLK tACS tACH AVD# tAVDP Addresses 555h PA VA
In Progress
Read Status Data
VA
Data tCAS CE#
A0h
PD tDS tDH
Complete
OE#
tCSW tWP
tCH
WE# tWHWH1 tWC tWPH
tVCS VCC
Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A21-A12 are don't care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 33.
Synchronous Program Operation Timings: WE# Latched Addresses
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INFORMATION
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tAVCH CLK tAS tAH AVD# tAVDP Addresses 555h PA VA
In Progress
Read Status Data
VA
Data tCAS CE#
A0h
PD tDS tDH
Complete
OE#
tCSW tWP
tCH
WE# tWHWH1 tWC tWPH
tVCS VCC
Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A21-A12 are don't care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 34.
Synchronous Program Operation Timings: CLK Latched Addresses
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INFORMATION
AC CHARACTERISTICS
VIH
Erase Command Sequence (last two cycles)
Read Status Data
CLK
VIL
tAVDP AVD# tAS Addresses 2AAh tAH SA
555h for chip erase 10h for chip erase
VA
In Progress
VA
Data
55h
30h tDS tDH
Complete
CE#
OE# tWP WE# tCS tVCS VCC
tCH
tWHWH2 tWPH tWC
Figure 35.
Notes: 1. SA is the sector address for Sector Erase.
Chip/Sector Erase Command Sequence
2. Address bits A21-A12 are don't cares during unlock cycles in the command sequence.
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INFORMATION
AC CHARACTERISTICS
CE#
AVD# WE# Addresses Data Don't Care A0h
PA Don't Care PD Don't Care
OE# ACC
VID
1 s
tVIDS tVID
VIL or VIH
Note: Use setup and hold times from conventional program operation.
Figure 36.
Accelerated Unlock Bypass Programming Timing
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INFORMATION
AC CHARACTERISTICS
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ
Data
Status Data
Status Data
Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 37.
Data# Polling Timings (During Embedded Algorithm)
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ
Data
Status Data
Status Data
Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 38.
Toggle Bit Timings (During Embedded Algorithm)
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INFORMATION
AC CHARACTERISTICS
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC tIACC Status Data Status Data
Data
RDY
Notes: 1. The timings are similar to synchronous read timings. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data.
Figure 39.
Synchronous Data Polling Timings/Toggle Bit Timings
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 40.
DQ2 vs. DQ6
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INFORMATION
AC CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RDY High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns s s
Note: Not 100% tested.
VID RESET# VIL or VIH tVIDR Program or Erase Command Sequence CE# tVIDR
VID
VIL or VIH
WE# tRSP RDY tRRB
Figure 41.
Temporary Sector Unprotect Timing Diagram
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ADVANCE
INFORMATION
AC CHARACTERISTICS
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Protect/Unprotect
Valid* Verify 40h
Sector Protect: 150 s Sector Unprotect: 15 ms
Valid*
Data 1 s CE#
60h
60h
Status
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 42. Sector/Sector Block Protect and Unprotect Timing Diagram
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INFORMATION
AC CHARACTERISTICS)
Address boundary occurs every 64 words, beginning at address 00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
C60 CLK Address (hex) AVD# 3C (stays high)
C61 3D
C62 3E
C63 3F
C63 3F
C63 3F
C64 40
C65 41
C66 42
C67 43
tRACC RDY(1) tRACC RDY(2)
latency latency
tRACC
tRACC
Data
D60
D61
D62
D63
D64
D65
D66
D67
Notes: 1. RDY active with data (A18 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing a bank in the process of performing an erase or program. 4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at the boundary crossing.
Figure 43.
Latency with Boundary Crossing
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INFORMATION
AC CHARACTERISTICS
Address boundary occurs every 64 words, beginning at address 00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
C60 CLK Address (hex) AVD# 3C (stays high)
C61 3D
C62 3E
C63 3F
C63 3F
C63 3F
C64 40
tRACC RDY(1) tRACC RDY(2)
latency latency
tRACC
tRACC
Data
D60
D61
D62
D63
Invalid
Read Status
OE#, CE#
(stays low)
Notes: 1. RDY active with data (A18 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program.
Figure 44. Latency with Boundary Crossing into Program/Erase Bank
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INFORMATION
AC CHARACTERISTICS
Data
D0
D1
AVD#
Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following AVD# falling edge
OE# 1 CLK 0 1 2 3
4
5
6
7
2
3
4
5
number of clock cycles programmed
Wait State Decoding Addresses: A14, A13, A12 = "111" Reserved A14, A13, A12 = "110" Reserved A14, A13, A12 = "101" 5 programmed, 7 total A14, A13, A12 = "100" 4 programmed, 6 total A14, A13, A12 = "011" 3 programmed, 5 total A14, A13, A12 = "010" 2 programmed, 4 total A14, A13, A12 = "001" 1 programmed, 3 total A14, A13, A12 = "000" 0 programmed, 2 total Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to "101".
Figure 45.
Example of Wait States Insertion
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INFORMATION
AC CHARACTERISTICS
Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence
tWC
tRC
tRC
tWC
CE#
OE# tOE tOEH WE# tWPH tWP tDS tDH Data
PD/30h RD
tGHWL
tACC
tOEZ tOEH
RD AAh
tSR/W Addresses
PA/SA RA RA 555h
tAS AVD# tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. The system should read status twice to ensure valid information.
Figure 46.
Back-to-Back Read/Write Cycle Timings
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INFORMATION
SRAM AC CHARACTERISTICS Read Cycle
Parameter Symbol tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH Description Read Cycle Time Address Access Time Chip Enable to Output Output Enable Access Time LB#s, UB#s to Access Time Chip Enable (CE1#s Low and CE2s High) to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#s, LB#s Disable to High-Z Output Output Disable to High-Z Output Output Data Hold from Address Change Min Max Max Max Max Min Min Min Max Max Max Min E6, E7, D6, D7 55 55 55 25 55 10 10 5 25 25 25 10 E8, E9, D8, D9 70 70 70 35 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
Figure 47.
SRAM Read Cycle--Address Controlled
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INFORMATION
SRAM AC CHARACTERISTICS
tRC Address tAA tCO1 tOH
CE#1s
CE2s
tCO2 tOE tOLZ tBLZ tLZ
tHZ
OE#
tOHZ Data Valid
Data Out
High-Z
Figure 48.
Notes: 1. WE# = VIH.
SRAM Read Cycle
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection.
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INFORMATION
SRAM AC CHARACTERISTICS Write Cycle
Parameter Symbol tWC tCw tAS tAW tBW tWP tWR tWHZ tDW tDH tOW Description Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write UB#s, LB#s to End of Write Write Pulse Time Write Recovery Time Write to Output High-Z Max Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Min Min min 20 30 0 5 ns ns ns Min Min Min Min Min Min Min Min 45 45 45 0 0 ns E6, E7, D6, D7 55 45 0 60 60 50 E8, E9, D8, D9 70 60 Unit ns ns ns ns ns ns ns
tWC Address tCW (See Note 1) tAW CE2s tCW (See Note 1) tWP (See Note 4) tAS (See Note 3) High-Z tWHZ Data Out Data Undefined tDW
Data Valid
tWR
CE1#s
WE#
tDH High-Z tOW
Data In
Notes: 1. WE# controlled. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write.
Figure 49.
SRAM Write Cycle--WE# Control
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INFORMATION
SRAM AC CHARACTERISTICS
tWC Address tAS (See Note 2 ) t CW (See Note 3) CE1#s tAW CE2s tBW tWP (See Note 5) WE# tDW Data In tDH tWR (See Note 4)
UB#s, LB#s
Data Valid
Data Out
High-Z
High-Z
Notes: 1. CE1#s controlled. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write.
Figure 50.
SRAM Write Cycle--CE1#s Control
October 23, 2003
Am42BDS6408H
83
ADVANCE
INFORMATION
SRAM AC CHARACTERISTICS
tWC Address tCW (See Note 2) tAW CE2s UB#s, LB#s tCW (See Note 2) tBW tAS (See Note 4) tWP (See Note 5) tDW Data In tDH tWR (See Note 3)
CE1#s
WE#
Data Valid
Data Out
High-Z
High-Z
Notes: 1. UB#s and LB#s controlled. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write.
Figure 51.
SRAM Write Cycle--UB#s and LB#s Control
84
Am42BDS6408H
October 23, 2003
ADVANCE
INFORMATION
ERASE AND PROGRAMMING PERFORMANCE
Parameter 32 Kword Sector Erase Time 4 Kword Chip Erase Time Word Programming Time Accelerated Word Programming Time Chip Programming Time (Note 3) Accelerated Chip Programming Time 0.2 54 9 4 38 17 210 120 114 50 5 s s s s s Excludes system level overhead (Note 5) Excludes system level overhead (Note 5) Typ (Note 1) 0.4 Max (Note 2) 5 s Excludes 00h programming prior to erasure (Note 4) Unit Comments
Notes: 1. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 1 million cycles. Additionally, programming typicals assumes a checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 1.65 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 16, "Command Definitions," on page 40 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1 million cycles.
BGA BALL CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 4.2 5.4 3.9 Max 5.0 6.5 4.7 Unit pF pF pF
Notes:
1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
October 23, 2003
Am42BDS6408H
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ADVANCE
INFORMATION
PHYSICAL DIMENSIONS TLB 089--89-ball Fine-Pitch Ball Grid Array (FBGA) 10 x 8 mm Package
D
0.15 C (2X)
10 9 8 7
A
D1 eD
SE
7
E eE
6 5 4 3 2 1 J H G F E D CB A
E1
INDEX MARK PIN A1 CORNER 10
K
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.08 C
SIDE VIEW b
89X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC TLB089 N/A 10.00 mm x 8.00 mm PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.33 MIN --0.20 0.81 NOM ------10.00 BSC. 8.00 BSC. 7.20 BSC. 7.20 BSC. 10 10 89 --0.80 BSC 0.80 BSC 0.40 BSC B10,C1,C10,D1,D10,G1,G10 H1,H10,J1,J10 0.43 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3294\ 16-038.22a
Note: BSC is an ANSI standard for Basic Space Centering
86
Am42BDS6408H
October 23, 2003
ADVANCE
INFORMATION
REVISION SUMMARY Revision A (July 14, 2003)
Initial release.
Revision A+1 (July 15, 2003)
Corrected Ordering Information OPNs.
Revision A+2 (July 21, 2003)
Corrected typos in datasheet regarding package name.
Revision A+3 (October 23, 2003)
Corrected globally all pSRAM to SRAM. Remove 80 MHz option throughout.
Trademarks Copyright (c) 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
October 23, 2003
Am42BDS6408H
87
Sales Offices and Representatives
North America
ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 5 6 ) 8 3 0 - 9 1 9 2 ARIZONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 6 0 2 ) 24 2 - 4 4 0 0 CALIFORNIA, Irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 4 9 ) 4 5 0 - 7 5 0 0 Sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 4 0 8 ) 7 3 2 - 24 0 0 COLORADO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 0 3 ) 74 1 - 2 9 0 0 CONNECTICUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 0 3 ) 2 6 4 - 7 8 0 0 FLORIDA, Clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 2 7 ) 7 9 3 - 0 0 5 5 Miami (Lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 0 5 ) 8 2 0 - 1 1 1 3 GEORGIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 7 0 ) 8 1 4 - 0 2 2 4 ILLINOIS, Chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 6 3 0 ) 7 7 3 - 4 4 2 2 MASSACHUSETTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 8 1 ) 2 1 3 - 6 4 0 0 MICHIGAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 4 8 ) 4 7 1 - 6 2 9 4 MINNESOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 6 1 2 ) 74 5 - 0 0 0 5 NEW JERSEY, Chatham . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 7 3 ) 7 0 1 - 1 7 7 7 NEW YORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 4 2 5 - 8 0 5 0 NORTH CAROLINA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 1 9 ) 8 4 0 - 8 0 8 0 OREGON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 0 3 ) 24 5 - 0 0 8 0 PENNSYLVANIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 1 5 ) 3 4 0 - 1 1 8 7 SOUTH DAKOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 6 0 5 ) 69 2 - 5 7 7 7 TEXAS, Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 1 2 ) 3 4 6 - 7 8 3 0 Dallas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 7 2 ) 9 8 5 - 1 3 4 4 Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 8 1 ) 3 76 - 8 0 8 4 VIRGINIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 0 3 ) 7 3 6 - 9 5 6 8
Representatives in U.S. and Canada
ARIZONA, Tempe - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 4 8 0 ) 8 3 9 - 2 3 2 0 CALIFORNIA, Calabasas - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 8 1 8 ) 8 7 8 - 5 8 0 0 Irvine - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 4 9 ) 2 6 1 - 2 1 2 3 San Diego - Centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 8 5 8 ) 2 7 8 - 4 9 5 0 Santa Clara - Fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 4 0 8 ) 3 5 0 - 4 8 0 0 CANADA, Burnaby, B.C. - Davetek Marketing. . . . . . . . . . . . . . . . . . . . ( 6 0 4 ) 4 3 0 - 3 6 8 0 Calgary, Alberta - Davetek Marketing. . . . . . . . . . . . . . . . . ( 4 0 3 ) 2 8 3 - 3 5 7 7 Kanata, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . . . ( 6 1 3 ) 5 9 2 - 9 5 4 0 Mississauga, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . ( 9 0 5 ) 6 7 2 - 2 0 3 0 St Laurent, Quebec - J-Squared Tech. . . . . . . . . . . . . . . . ( 5 1 4 ) 7 4 7 - 1 2 1 1 COLORADO, Golden - Compass Marketing . . . . . . . . . . . . . . . . . . . . . . ( 3 0 3 ) 2 7 7 - 0 4 5 6 FLORIDA, Melbourne - Marathon Technical Sales . . . . . . . . . . . . . . . . ( 3 2 1 ) 7 2 8 - 7 7 0 6 Ft. Lauderdale - Marathon Technical Sales . . . . . . . . . . . . . . ( 9 5 4 ) 5 2 7 - 4 9 4 9 Orlando - Marathon Technical Sales . . . . . . . . . . . . . . . . . . ( 4 0 7 ) 8 7 2 - 5 7 7 5 St. Petersburg - Marathon Technical Sales . . . . . . . . . . . . . . ( 7 2 7 ) 8 9 4 - 3 6 0 3 GEORGIA, Duluth - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . ( 6 7 8 ) 5 8 4 - 1 1 2 8 ILLINOIS, Skokie - Industrial Reps, Inc. . . . . . . . . . . . . . . . . . . . . . . . . ( 8 4 7 ) 9 6 7 - 8 4 3 0 INDIANA, Kokomo - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 6 5 ) 4 5 7 - 7 2 4 1 IOWA, Cedar Rapids - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . ( 3 1 9 ) 2 9 4 - 1 0 0 0 KANSAS, Lenexa - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 1 3 ) 4 6 9 - 1 3 1 2 MASSACHUSETTS, Burlington - Synergy Associates . . . . . . . . . . . . . . . . . . . . . ( 7 8 1 ) 2 3 8 - 0 8 7 0 MICHIGAN, Brighton - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 8 1 0 ) 2 2 7 - 0 0 0 7 MINNESOTA, St. Paul - Cahill, Schmitz & Cahill, Inc. . . . . . . . . . . . . . . . . . ( 6 5 1 ) 69 9 - 0 2 0 0 MISSOURI, St. Louis - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 1 4 ) 9 9 7 - 4 5 5 8 NEW JERSEY, Mt. Laurel - SJ Associates . . . . . . . . . . . . . . . . . . . . . . . . . ( 8 5 6 ) 8 6 6 - 1 2 3 4 NEW YORK, Buffalo - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 7 4 1 - 7 1 1 6 East Syracuse - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . ( 3 1 5 ) 4 3 7 - 8 3 4 3 Pittsford - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 5 8 6 - 3 6 6 0 Rockville Centre - SJ Associates . . . . . . . . . . . . . . . . . . . . ( 5 1 6 ) 5 3 6 - 4 2 4 2 NORTH CAROLINA, Raleigh - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . . ( 9 1 9 ) 8 4 6 - 5 7 2 8 OHIO, Middleburg Hts - Dolfuss Root & Co. . . . . . . . . . . . . . . . . ( 4 4 0 ) 8 1 6 - 1 6 6 0 Powell - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . . ( 6 1 4 ) 7 8 1 - 0 7 2 5 Vandalia - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . ( 9 3 7 ) 8 9 8 - 9 6 1 0 Westerville - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . ( 6 1 4 ) 5 2 3 - 1 9 9 0 OREGON, Lake Oswego - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . ( 5 0 3 ) 6 7 0 - 0 5 5 7 UTAH, Murray - Front Range Marketing . . . . . . . . . . . . . . . . . . . . ( 8 0 1 ) 2 8 8 - 2 5 0 0 VIRGINIA, Glen Burnie - Coherent Solution, Inc. . . . . . . . . . . . . . . . . ( 4 1 0 ) 7 6 1 - 2 2 5 5 WASHINGTON, Kirkland - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . ( 4 2 5 ) 8 2 2 - 9 2 2 0 WISCONSIN, Pewaukee - Industrial Representatives . . . . . . . . . . . . . . . . ( 2 6 2 ) 5 74 - 9 3 9 3
International
AUSTRALIA, North Ryde . . . . . . . . . . . . . . . . . . . . . . . T E L ( 6 1 ) 2 - 8 8 - 7 7 7 - 2 2 2 BELGIUM, Antwerpen . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 2 ) 3 - 2 4 8 - 4 3 - 0 0 BRAZIL, San Paulo . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 5 5 ) 1 1 - 5 5 0 1 - 2 1 0 5 CHINA, Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 6 ) 1 0 - 6 5 1 0 - 2 1 8 8 Shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 6 ) 2 1 - 6 3 5 - 0 0 8 3 8 Shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 6 ) 7 5 5 - 24 6 - 1 5 5 0 FINLAND, Helsinki . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 5 8 ) 8 8 1 - 3 1 1 7 FRANCE, Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 3 ) - 1 - 4 9 7 5 1 0 1 0 GERMANY, Bad Homburg . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 9 ) - 6 1 7 2 - 9 2 6 7 0 Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 9 ) - 8 9 - 4 5 0 5 3 0 HONG KONG, Causeway Bay . . . . . . . . . . . . . . . . . . . T E L ( 8 5 ) 2 - 2 9 5 6 - 0 3 8 8 ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 9 ) - 0 2 - 3 8 1 9 6 1 INDIA, New Delhi . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 9 1 ) 1 1 - 6 2 3 - 8 6 2 0 JAPAN, Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 1 ) 6 - 6 2 4 3 - 3 2 5 0 Tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 1 ) 3 - 3 3 4 6 - 7 6 0 0 KOREA, Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 2 ) 2 - 3 4 6 8 - 2 6 0 0 RUSSIA, Moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(7)-095-795-06-22 SWEDEN, Stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 6 ) 8 - 5 62 - 5 4 0 - 0 0 TAIWAN,Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 8 6 ) 2 - 8 7 7 3 - 1 5 5 5 UNITED KINGDOM, Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 4 ) 1 2 7 6 - 8 0 3 1 0 0 Haydock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 4 ) 1 9 4 2 - 2 7 2 8 8 8
es
Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics.The performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. For specific testing details, contact your local AMD sales representative.The company assumes no responsibility for the use of any circuits described herein. (c) Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo and combination thereof, are trademarks of Advanced Micro Devices, Inc. Other product names are for informational purposes only and may be trademarks of their respective companies.
Representatives in Latin America
ARGENTINA, Capital Federal Argentina/WW Rep. . . . . . . . . . . . . . . . . . . .54-11)4373-0655 CHILE, Santiago - LatinRep/WWRep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993 COLUMBIA, Bogota - Dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 7 1 ) 4 1 0 - 4 1 8 2 MEXICO, Guadalajara - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 5 2 3 ) 8 1 7 - 3 9 0 0 Mexico City - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 5 2 5 ) 7 5 2 - 2 7 2 7 Monterrey - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . . ( 5 2 8 ) 3 69 - 6 8 2 8 PUERTO RICO, Boqueron - Infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 8 7 ) 8 5 1 - 6 0 0 0
One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400 TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com
(c)2003 Advanced Micro Devices, Inc. 01/03 Printed in USA

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